Integrated circuit (IC) technologies are constantly being improved. Such improvements frequently involve scaling down device geometries to achieve lower fabrication costs, higher device integration density, higher speeds, and better performance. Photolithography is frequently used for forming components of an integrated circuit device. Generally, an exposure tool passes light through a photomask or reticle and focuses the light onto a photosensitive layer of a wafer, resulting in the photosensitive layer having an image of IC features therein. The photosensitive layer is then developed, such that a patterned photosensitive layer is formed that includes a pattern of the IC features. This pattern may then be transferred to the wafer, such that the IC features may be formed in the wafer. It has been observed that printing IC features having varying dimensions is presently limited by lithography material properties and/or lithography process characteristics. Accordingly, although existing approaches for patterning IC features have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.